3

Design for DES Key Search Array Chip-Level Specification

In This chapter:

• ASIC Description

• Board description

• Read and Write Timing

• Addressing Registers

• All-active Signal

• ASIC Register Allocation

Advanced Wireless Technologies, Inc.
and
Cryptography Research

ASIC Description

Select1

Selects Cipher text 1

C0

Cipher text 0

C1

Cipher text 1

Search

Search is active

K

Key

Mask

Plain text bit mask and DES output

Match=0

a Zero is found in any bit position of plain text vector as specified in step 4 of Search Unit Operation (see Chapter 2)

CBC & Extra XOR

Perform step 3 of Search Unit Operation (see Chapter 2)

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Figure 3-1. Search Unit Operation Flow Chart

To determine the maximum number of bit required for the Key:

K= log₂(Maximum combinations/number of chips)

= log₂(2⁵⁶/(24 cpc * 64 cpb * 24 boards) = log₂(1. 95E12) = 42 bits

If we are going to use 32-bit counters, then it will overflow every:

2³² * 16 cycles * 25ns = 1. 72 * 10¹²ns = 1720 sec = 28. 7 minutes

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Figure 3-2 State Diagram tor the Search Unit

Board description

The PC will interface with the ASICs through a parallel card. The parallel card has three ports, assigned:

Port A: Address(7:0)
Port B: Data(7:0)
Port C: Control, 8 signals

To reduce the routing resources on the boards and ASICs we multiplex the address lines. To access register on the ASIC, it is required that the software latch the

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Figure 3-3: Search Unit's Block Diagram

address three times: Board-ID(7:0), Chip-ID(6:0) and then Register address.

Having switches on the board makes the design flexible and expandable. Each board has its own unique Board-ID configured on switches: for example a board

3-5

with an ID of hexadecimal 5F has its board ID switches configured as follows:

Read and Write Timing

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t_as1 10 ns Min Board-ID and Chip-ID Address setup

t_as2 10 ns Min Write Register-Address setup

t_as3 10 ns Min Read Register-Address setup

t_ah1 10 ns Min Board-ID and Chip-ID Address invalid (hold)

t_ah2 10 ns Min Write strobe trailing edge to Address invalid (hold)

t_av 10 ns Min ALE valid

t_ds 10 ns Min Data valid to Write strobe goes low (setup)

t_ch 10 ns Min Chip select hold

t_dh 10 ns Min Write strobe goes high to data invalid (Data hold)

t_rv 10 ns Min Read strobe duration

t_dv 100 ns Max Read strobe goes low to data valid

t_dh 100 ns Max Read strobe goes high to data invalid (Data hold)

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Addressing Registers

Figure 3-4 Address Bus Scheme

All-active Signal

If low the SearchActive bit together. We will place one AND gate per ASIC and cascade them.

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ASIC Register Allocation

Number of register required:

58 common registers + 8 * n registers; n = the total number of search units in an ASIC In this case n = 24, therefore 58 + 192 = 250 registers

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Note: The unspecified pins are Non-Connects

CNTRL0 = ALE = ADDSEL1

CNTRL1 = CSB = ADDSEL2